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ВКР Магистра. Программный сложно-функциональный блок


НазваниеПрограммный сложно-функциональный блок
Дата08.10.2019
Размер2.06 Mb.
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Имя файлаВКР Магистра.PDF
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ТипПрограмма
#65602
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ПРИЛОЖЕНИЕ А
//-------СФБУТ-------//
`timescale 1 ps / 1 ps module Automat_11
(SDA,CLK,SCL,sensor1,sensor2,sensor3,sensor4,sensor5,sensor6,sensor7,sensor8,sensor1a,sensor2a,se nsor3a,sensor4a,sensor5a,sensor6a,sensor7a,sensor8a, IO1,IO2,IO3,IO4, nCE1_1,nCE2_1,nOE_1, nCE1_2,nCE2_2,nOE_2,nCE1_3,nCE2_3,nOE_3, nCE1_4
,nCE2_4,nOE_4,SO,SI1,SI2,SI3,SI4,nCS_1,nWP_1,nCS_2,nWP_2,nCS_3,nWP_3,nCS_4,nWP_4,clk_out_memrr2u,
ADDR, clck_on ); inout wire SDA;//Шины i2c// inout wire SCL; input wire CLK; inout wire [7:0] IO1; inout wire [7:0] IO2; inout wire [7:0] IO3; inout wire [7:0] IO4; input wire sensor1;//Подключение датчиков через компараторы// input wire sensor2; input wire sensor3; input wire sensor4; input wire sensor5; input wire sensor6; input wire sensor7; input wire sensor8; input wire [15:0] sensor1a; //Подключение датчиков через АЦП// input wire [15:0] sensor2a; input wire [15:0] sensor3a; input wire [15:0] sensor4a; input wire [15:0] sensor5a; input wire [15:0] sensor6a; input wire [15:0] sensor7a; input wire [15:0] sensor8a; input wire SI1;// Последовательные выводы данных для 1661РР2У// input wire SI2; input wire SI3; input wire SI4; output wire nCE1_1;// Сигналы разрешения// output wire nCE2_1; output wire nOE_1; output wire nCE1_2; output wire nCE2_2; output wire nOE_2; output wire nCE1_3; output wire nCE2_3; output wire nOE_3; output wire nCE1_4; output wire nCE2_4; output wire nOE_4; output wire SO; output wire nCS_1; output wire nWP_1; output wire nCS_2; output wire nWP_2; output wire nCS_3; output wire nWP_3; output wire nCS_4; output wire nWP_4; output wire clk_out_memrr2u; // вывод тактового сигнала для 1661РР2У// output wire[16:0] ADDR;//Вывод адреса для 1666РЕ014// wire [7:0] PIn1; wire [7:0] PIn2; wire [7:0] PIn3; wire [7:0] PIn4; wire Cselect1 ; /// wire Cselect2 ; wire Cselect3 ; wire Cselect4 ; wire out1; wire out2; wire sda_out; wire scl_out;
82 wire enable1; wire enable2; wire tristate_usl; wire tristate_usl_scl; wire read_int_mem; wire sel; wire ram_select; input wire clck_on; wire [7:0] IOout1;//Выводы данных для 1666РЕ014// wire [7:0] IOout2; wire [7:0] IOout3; wire [7:0] IOout4; wire [7:0] INio; wire [7:0] INOUTio; wire [7:0] OUTio; wire enableio;
//---------------------Подключения буферов трех состояний---// tri_buf tribuf_SDA (
.INOUT(SDA),
.OUT(out1),
.IN(sda_out),
.enable(enable1)); tri_buf tribuf_SCL (
.INOUT(SCL),
.OUT(out2),
.IN(scl_out),
.enable(enable2)); tri_bufIO tribuf_IO1 (
.INOUTio(IO1),
.OUTio(PIn1),
.INio(IOout1),
.enableio(enbufIO1)); tri_bufIO tribuf_IO2(
.INOUTio(IO2),
.OUTio(PIn2),
.INio(IOout2),
.enableio(enbufIO1)); tri_bufIO tribuf_IO3 (
.INOUTio(IO3),
.OUTio(PIn3),
.INio(IOout3),
.enableio(enbufIO3)); tri_bufIO tribuf_IO4 (
.INOUTio(IO4),
.OUTio(PIn4),
.INio(IOout4),
.enableio(enbufIO4));
I2CslaveWith8bitsIO i2c(
.clk(clk),
.sda_in(out1),
.sda_out(sda_out),
.tristate_usl(enable1),
.scl_in(out2),
.scl_out(scl_out),
.tristate_usl_scl(enable2),
.sensor1_1(sensor1),
.sensor2_1(sensor2),
.sensor3_1(sensor3),
.sensor4_1(sensor4),
.sensor5_1(sensor5),
.sensor6_1(sensor6),
.sensor7_1(sensor7),
.sensor8_1(sensor8),
.sensor1_1a(sensor1a),
.sensor2_1a(sensor2a),
.sensor3_1a(sensor3a),
.sensor4_1a(sensor4a),
.sensor5_1a(sensor5a),
.sensor6_1a(sensor6a),
.sensor7_1a(sensor7a),
.sensor8_1a(sensor8a),
. IOout1(IOout1),
83
. IOout2(IOout2),
. IOout3(IOout3),
. IOout4(IOout4),
.nCE1_1(nCE1_1),
.nCE2_1(nCE2_1),
.nOE_1(nOE_1),
.nCE1_2(nCE1_2),
.nCE2_2(nCE2_2),
.nOE_2(nOE_2),
.nCE1_3(nCE1_3),
.nCE2_3(nCE2_3),
.nOE_3(nOE_3),
.nCE1_4(nCE1_4),
.nCE2_4(nCE2_4),
.nOE_4(nOE_4),
.SO(SO),
.SI1(SI1),
.SI2(SI2),
.SI3(SI3),
.SI4(SI4),
.PIn1(PIn1),
.PIn2(PIn2),
.PIn3(PIn3),
.PIn4(PIn4),
.nCS_1(nCS_1),
.nWP_1(nWP_1),
.nCS_2(nCS_2),
.nWP_2(nWP_2),
.nCS_3(nCS_3),
.nWP_3(nWP_3),
.nCS_4(nCS_4),
.nWP_4(nWP_4),
.clk_out_memrr2u(clk_out_memrr2u),
.ADDR(ADDR),
.enbufIO1(enbufIO1),
.enbufIO2(enbufIO2),
.enbufIO3(enbufIO3),
.enbufIO4(enbufIO4)); clckEN clckENmy (
.clk(clk),
.CLK(CLK),
.clck_on(clck_on)); endmodule module tri_buf(IN,INOUT,OUT,enable); input wire IN; input wire enable; inout wire INOUT; output reg OUT; assign INOUT=(enable== 1'b1) ? 1'bz : IN; always @(*) OUT= INOUT; endmodule module tri_bufIO(INio,INOUTio,OUTio,enableio); input wire [7:0] INio; input wire enableio; inout wire [7:0] INOUTio; output reg [7:0] OUTio; assign INOUTio=(enableio== 1'b1) ? 1'bz : INio; always @(*) OUTio= INOUTio; endmodule module clckEN (CLK,clck_on,clk); input wire CLK; input wire clck_on; output wire clk; assign clk = (clck_on) ? CLK:1'b0 ; endmodule
//------СФБУТ с односторонними выводами--// module I2CslaveWith8bitsIO(sda_in, scl_in,clk, sda_out,scl_out,tristate_usl, tristate_usl_scl,sensor1_1,sensor2_1,sensor3_1,sensor4_1,sensor5_1, sensor6_1,sensor7_1,sensor8_1,sensor1_1a,sensor2_1a,sensor3_1a,sensor4_1a, sensor5_1a,sensor6_1a,sensor7_1a,sensor8_1a, IOout1,IOout2,
IOout3, IOout4 ,nCE1_1,nCE2_1,nOE_1, nCE1_2,nCE2_2,nOE_2,nCE1_3,nCE2_3, nOE_3, nCE1_4,nCE2_4,nOE_4, SO,SI1,SI2,SI3,SI4, PIn1,PIn2,PIn3,PIn4,
84 nCS_1,nWP_1,nCS_2,nWP_2,nCS_3,nWP_3,nCS_4,nWP_4,clk_out_memrr2u,ADDR ,enbufIO1,enbufIO2, enbufIO3, enbufIO4 );
//-----Описание сигналов-------// output wire [7:0] IOout1; output wire [7:0] IOout2; output wire [7:0] IOout3; output wire [7:0] IOout4; output wire nCE1_1; output wire nCE2_1; output wire nOE_1; output wire nCE1_2; output wire nCE2_2; output wire nOE_2; output wire nCE1_3; output wire nCE2_3; output wire nOE_3; output wire nCE1_4; output wire nCE2_4; output wire nOE_4; output wire enbufIO1; output wire enbufIO2; output wire enbufIO3; output wire enbufIO4; output wire SO; output wire nCS_1; output wire nWP_1; output wire nCS_2; output wire nWP_2; output wire nCS_3; output wire nWP_3; output wire nCS_4; output wire nWP_4; output wire clk_out_memrr2u; output sda_out; output scl_out; output tristate_usl; output tristate_usl_scl; output [15:0] ADDR; input wire SI1; input wire SI2; input wire SI3; input wire SI4; input wire [7:0] PIn1; input wire [7:0] PIn2; input wire [7:0] PIn3; input wire [7:0] PIn4; input sda_in; input scl_in; input clk; input sensor1_1; input sensor2_1; input sensor3_1; input sensor4_1; input sensor5_1; input sensor6_1; input sensor7_1; input sensor8_1; input [15:0] sensor1_1a; input [15:0] sensor2_1a; input [15:0] sensor3_1a; input [15:0] sensor4_1a; input [15:0] sensor5_1a; input [15:0] sensor6_1a; input [15:0] sensor7_1a; input [15:0] sensor8_1a; wire sel; wire [7:0] dat1; wire [7:0] dat2; wire [7:0] dat3; wire [7:0] dat4; wire [7:0] dat5; wire [7:0] dat6; wire [7:0] N_sens; wire [7:0] cnt_numb_event; wire select_RPO; wire [7:0] value; wire[7:0] data_RPO;
85 wire incycle; wire [8:0] cnt_RPO; wire write_success; wire linefree; wire event1; wire [2:0] select_mem; wire memerror; wire ram_select; wire SDA_shadow; wire start_or_stop; wire SDA_shadow_del; wire SDA_shadow_del_2 ; wire sda_in;
ODSKmy ODSK(
.sda_in(sda_in),
.scl_in(scl_in),
.clk(clk),
.sda_out(sda_out),
.scl_out(scl_out),
.tristate_usl(tristate_usl),
.tristate_usl_scl(tristate_usl_scl),
.event1(event1),
.N_sens(N_sens),
.dat1(dat1),
.dat2(dat2),
.dat3(dat3),
.cnt_numb_event(cnt_numb_event),
.dat4(dat4),
.dat5(dat5),
.dat6(dat6),
.value(value),
.data_RPO(data_RPO),
.incycle(incycle),
.cnt_RPO(cnt_RPO),
.read_int_mem(read_int_mem),
.write_success(write_success),
.linefree(linefree),
.select_mem(select_mem),
.memerror(memerror),
.sel(sel),
.ram_select(ram_select));
//-----------------Подключения ТОДМ--------//
TODMmy TODM(
.sensor1_1(sensor1_1),
.sensor2_1(sensor2_1),
.sensor3_1(sensor3_1),
.sensor4_1(sensor4_1),
.sensor5_1(sensor5_1),
.sensor6_1(sensor6_1),
.sensor7_1(sensor7_1),
.sensor8_1(sensor8_1),
.sensor1_1a(sensor1_1a),
.sensor2_1a(sensor2_1a),
.sensor3_1a(sensor3_1a),
.sensor4_1a(sensor4_1a),
.sensor5_1a(sensor5_1a),
.sensor6_1a(sensor6_1a),
.sensor7_1a(sensor7_1a),
.sensor8_1a(sensor8_1a),
.clk(clk),
.event1(event1),
.N_sens(N_sens),
.dat1(dat1),
.dat2(dat2),
.dat3(dat3),
.cnt_numb_event(cnt_numb_event),
.linefree(linefree));
//------------------ Подключения РПО--------//
RPOmy RPO(
.clk(clk),
.dat4(dat4),
.dat5(dat5),
.dat6(dat6),
.value(value),
.data_RPO(data_RPO),
.incycle(incycle),
.cnt_RPO(cnt_RPO),
86
.read_int_mem(read_int_mem),
.write_success(write_success),
.select_mem(select_mem),
.memerror(memerror),
. IOout1(IOout1),
. IOout2(IOout2),
. IOout3(IOout3),
. IOout4(IOout4),
.nCE1_1(nCE1_1),
.nCE2_1(nCE2_1),
.nOE_1(nOE_1),
.nCE1_2(nCE1_2),
.nCE2_2(nCE2_2),
.nOE_2(nOE_2),
.nCE1_3(nCE1_3),
.nCE2_3(nCE2_3),
.nOE_3(nOE_3),
.nCE1_4(nCE1_4),
.nCE2_4(nCE2_4),
.nOE_4(nOE_4),
.SO(SO),
.SI1(SI1),
.SI2(SI2),
.SI3(SI3),
.SI4(SI4),
.PIn1(PIn1),
.PIn2(PIn2),
.PIn3(PIn3),
.PIn4(PIn4),
.nCS_1(nCS_1) ,
.nWP_1(nWP_1),
.nCS_2(nCS_2),
.nWP_2(nWP_2),
.nCS_3(nCS_3),
.nWP_3(nWP_3),
.nCS_4(nCS_4),
.nWP_4 (nWP_4),
.clk_out_memrr2u(clk_out_memrr2u),
.ADDR (ADDR),
.enbufIO1(enbufIO1),
.enbufIO2(enbufIO2),
.enbufIO3(enbufIO3),
.enbufIO4(enbufIO4));
//-- 7 БИТНЫЙ АДРЕС СФБУТ-----// parameter I2C_ADR = 7'h51; parameter N= 3; //// bit adres v flash endmodule
//--------------------------------------------Модуль ОДСК-----------------------------------// module ODSKmy(sda_in, scl_in,clk, sda_out,scl_out,tristate_usl, tristate_usl_scl,event1, N_sens,dat1,dat2,dat3,cnt_numb_event,dat4,dat5,dat6,value, data_RPO,incycle,cnt_RPO,read_int_mem,write_success, linefree,select_mem,memerror,sel,ram_select);//comm output reg[7:0] N_sens;//---- Номер датчика---// output scl_out; output tristate_usl; output tristate_usl_scl; output reg [7:0] value; output wire [7:0] data_RPO; output reg incycle; output reg linefree output wire [2:0] select_mem ;//--Выбор номера памяти--// output wire read_int_mem; input memerror; reg sensormode1=1'b0; input [7:0] dat1;//----Информац Сигналы от ТОДМ и РПО input [7:0] dat2; input [7:0] dat3; input [7:0] dat4; input [7:0] dat5; input [7:0] dat6; input event1; input sda_in; input scl_in; input clk;
87 input wire [7:0] cnt_numb_event; input wire write_success; wire [7:0] dat11; wire [7:0] dat21; wire [7:0] dat31; wire SDA_shadow; wire start_or_stop; wire SDA_shadow_del; wire SDA_shadow_del_2 ; wire sda_in; parameter I2C_ADR = 7'h51; parameter N= 3; //// bit adres v flas reg select_RPO=1'b0; reg [7:0] I2C_ADR_ustr=I2C_ADR; reg [7:0] data_1=1'b0; reg [7:0] data_2=1'b0; reg [7:0] data_3=0; reg [3:0] bitcnt; reg data_phase; reg SDAr; reg [7:0] mem; reg [7:0] mem_0; reg [7:0] numb_query; reg [6:0] addr_syst_cntrl; reg [6:0] addr_syst_cntrl_fix = 7'h04;//---фиксированый адрес СК. reg [7:0] type_query; reg[8:0] new_bitcnt; reg[3:0] new_bitcnt_transmit=4'h8; reg [7:0] number_sensor;//Регистр Номер датчика--// reg adr_match,op_read, got_ACK; reg new1=1'b0; reg [3:0] bitcnt_transmit; reg flag_rw=1'b0; reg[7:0] CRCout=1'b0; ;//--Входн CRC ---// reg [7:0] type_response;//--Регистр тип ответа---// reg[7:0] CRCin=1'b0; reg crceq =1'b0; reg [7:0] cnt_crc; reg stopcrc; reg stopcrc_sob; assign dat11= dat1; assign dat21= dat2; assign dat31= dat3; reg [19:0] addr; reg [8:0] cnt_mem2=9'd256; reg [7:0] cnt_mem1; reg linefree1=1'b0; reg stopans1=1'b0; reg stopans; reg [7:0] numb_bit_cnt; reg [7:0] crc_calc; reg [7:0] crc_reciv; reg [7:0] data; reg stopcrc_ans; reg crcneq; reg tts; reg start_answer_sensors; wire bit_DATA =

bitcnt[3]; assign select_mem = (type_query[3]==2'b1& !event1 & !crcneq) ? type_query [2:0]: 1'b0; assign read_int_mem = (select_RPO)? crceq: 1'b0; assign data_RPO= (select_RPO) ? mem_0: 1'b0; assign #3000000 sda_in1 = sda_in; assign sda_out1= (new1) ? tristate_usl : sda_out; assign bitctk =(!new1 & bitcnt_transmit==4'h7 & new_bitcnt_transmit<4'h7 )? 1'b1: 1'b0 ; assign #1 SDA_shadow = (scl_in | start_or_stop) ? sda_in1 : SDA_shadow; assign #1 start_or_stop = scl_in ? 1'b0 : (sda_in1 ^ SDA_shadow); assign #3000000 bit_DATA1 = bit_DATA; always @ (negedge clk) if (!new1 | incycle) begin linefree= 1'b0; end else begin linefree= 1'b1; end always @(posedge clk)
88 if (select_RPO) begin value<=numb_bit_cnt; end else begin value=1'b0; end
//--------------------------------------------------------------------------------------// always @(negedge scl_in or posedge start_or_stop) if(start_or_stop) incycle <= 1'b0; else if(sda_in1) incycle <= 1'b1;
// the DATA bits are the first 8 bits sent wire bit_ACK = bitcnt[3]; // the ACK bit is the 9th bit sent always @(negedge scl_in or negedge incycle) if(incycle) begin bitcnt <= 4'h7; // the bit 7 is received first data_phase <= 1'b0; end else begin if(bit_ACK) begin bitcnt <= 4'h7; data_phase <= 1'b1; end else bitcnt <= bitcnt - 4'h1; end
//---------------------------------------------------------------------------------------------------------------------------//
// and detect if the I2C address matches our own wire adr_phase = data_phase; always @(posedge scl_in) SDAr<=sda_in1; // sample SDA on posedge since the I2C spec specifies as low as 0µs hold-time on negedge wire op_write = op_read; always @(negedge scl_in or negedge incycle) if(incycle) begin got_ACK <= 1'b0; adr_match <= 1'b1; op_read <= 1'b0; end else begin if(adr_phase & bitcnt==7 & SDAr!=I2C_ADR[6]) adr_match<=1'b0; if(adr_phase & bitcnt==6 & SDAr!=I2C_ADR[5]) adr_match<=1'b0; if(adr_phase & bitcnt==5 & SDAr!=I2C_ADR[4]) adr_match<=1'b0; if(adr_phase & bitcnt==4 & SDAr!=I2C_ADR[3]) adr_match<=1'b0; if(adr_phase & bitcnt==3 & SDAr!=I2C_ADR[2]) adr_match<=1'b0; if(adr_phase & bitcnt==2 & SDAr!=I2C_ADR[1]) adr_match<=1'b0; if(adr_phase & bitcnt==1 & SDAr!=I2C_ADR[0]) adr_match<=1'b0; if(adr_phase & bitcnt==0) op_read <= SDAr; if(bit_ACK) got_ACK <= SDAr; // we monitor the ACK to be able to free the bus when the master doesn't ACK during a read operation if(adr_match & bit_DATA & data_phase & op_write) mem[bitcnt] <= SDAr; // memory write end wire mem_bit_low = mem[bitcnt[2:0]]; wire SDA_assert_low = adr_match & bit_DATA & data_phase & op_read & mem_bit_low & got_ACK; wire SDA_assert_ACK = adr_match & bit_ACK & (adr_phase | op_write); wire SDA_low = SDA_assert_low | SDA_assert_ACK; output wire [8:0] cnt_RPO; assign cnt_RPO= (select_RPO) ? new_bitcnt : 1'b0;
//-----------------------NEW_COUNTER------------------// always @(posedge SDA_low) begin if(data_phase ) new_bitcnt <= 9'd260; else new_bitcnt <= new_bitcnt-3'd1;
89 end always @(posedge SDA_low) begin mem_0 <= mem; end wire bit_ACK_transmit;
//-------------------------Запись в регистры---------------------// always @(posedge SDA_low or posedge bit_ACK_transmit) begin case (new_bitcnt )
9'd259 : numb_query <= mem_0;
9'd258 : addr_syst_cntrl <= mem_0;
9'd257 : type_query <= mem_0;
9'd256 : number_sensor <= mem_0; endcase end always @( negedge clk) if (type_query[3:2]==2'b01) begin
N_sens <= number_sensor ; end else begin
N_sens<=1'b0; end
//-------------------------------Формирование ответа /----------------------------------------------------// assign clk_all= (incycle )? scl_in : clk ; always @(posedge write_success or posedge new_bitcnt_transmit[3] or posedge crcneq or posedge event1 or posedge memerror or posedge start_answer_sensors) begin new1<=new1; end always @(negedge clk_all ) if(new1 ) begin bitcnt_transmit <= 4'hf; // end else begin if(bit_ACK_transmit ) begin bitcnt_transmit <= 4'h7; end else bitcnt_transmit <= bitcnt_transmit - 4'h1; end assign bit_ACK_transmit=(new1) ? 1'b1: bitcnt_transmit[3]; always @(negedge bitcnt_transmit[3] )///// zamenit na vhodn sda potom if( new1) begin new_bitcnt_transmit <= 4'h8; // end else begin if( new_bitcnt_transmit !=4'b0) begin new_bitcnt_transmit <= new_bitcnt_transmit-3'h1; end else new_bitcnt_transmit <= 4'h8; end
//------------------- Интерпритатор запрса----------------------------// wire [7:0] numbqvorsob; assign numbqvorsob = (event1 ) ? cnt_numb_event : numb_query;
90 reg numb_or_value=1'b0; wire[7:0] number_or_value2; assign number_or_value2 [7:0] =(numb_or_value) ? 8'd255 : numb_bit_cnt[7:0]; output wire sel; assign sel = (read_int_mem & !write_success )? 1'b1:1'b0;
//-----------------------------------------------------------------/ always @(negedge clk) begin if (crcneq) begin data_2<=1'b0; data_1<=1'b0; data_3<=1'b0; end if (event1) begin data_1<=dat11; data_2<=dat21; data_3<=dat31; end if (type_query[3:2]==2'b10& !event1 & !crcneq ) begin //& crceq ) begin //--komanda zapisi v mem data_1 <= dat4; data_2<=dat5; data_3<=dat6; numb_or_value <=1'b0; select_RPO<=1'b1; end if (type_query[3:2]==2'b01 & !crcneq) //& !event1 ) //!crcneq) begin //--komanda zaprosa dannih s datchica begin numb_or_value<=1'b1; select_RPO<=1'b0; if (sensormode1) begin data_1<=dat11; data_2<=dat21; data_3<=dat31; end if (!sensormode1) begin data_1<=dat11; data_2<=dat21; data_3<=dat31; end end end
//--------------------Типы ответа--------------------------------------------------------------// always @(negedge clk) begin if (type_query[3:2]==2'b10 ) begin if (write_success) type_response <=3'b100;//----standartn sost--------------// if (memerror) type_response <=4'b1000; if (event1) type_response <=2'b10;//---esli sobitye-------// if (crcneq) type_response <=3'b11; end if (type_query[3:2]==2'b01) begin if (sensormode1 &
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