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ВКР Магистра. Программный сложно-функциональный блок


НазваниеПрограммный сложно-функциональный блок
Дата08.10.2019
Размер2.06 Mb.
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Имя файлаВКР Магистра.PDF
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ТипПрограмма
#65602
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event1 &

crcneq) type_response <=2'b00; if (!sensormode1 ) type_response <=2'b00;//----standartn sost--------------// if (event1) type_response <=2'b10;//---esli sobitye-------// if (crcneq) type_response <=2'b11; end end
//-----------------------Вывод на шину SDA----------------------// always @( negedge clk_all) begin if (new1) begin
91
//------------------------Вывод в заголовок ответа данных из регистров// if ( bitcnt_transmit==4'h7 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[6]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[5]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[4]; if ( bitcnt_transmit==3'h4 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[3]; if ( bitcnt_transmit==4'h3 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[2]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[1]; if ( bitcnt_transmit==3'h1 & new_bitcnt_transmit==7 ) sda_out <= addr_syst_cntrl[0]; if ( bitcnt_transmit==3'h0 & new_bitcnt_transmit==7 ) sda_out <= 1'b0; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==7 ) sda_out <= 1'b0;
//-------------Номер запроса в sda_out--------------------------// if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==6 ) sda_out <= numbqvorsob[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==6 ) sda_out <= 1'b0;
//-------------Адрес устройства в sda_out------------------------// if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==5 ) sda_out <= I2C_ADR_ustr[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==5 ) sda_out <= 1'b0;
//--------------Тип ответа в sda_out---------------------------// if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==4 ) sda_out <= type_response[7];//-----type response change if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==4 ) sda_out <= type_response[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==4 ) sda_out <= type_response[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==4 ) sda_out <= type_response[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==4 ) sda_out <= type_response[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==4 ) sda_out <= type_response[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==4 ) sda_out <= type_response[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==4 ) sda_out <= type_response[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==4 ) sda_out <= 1'b0;
//-------------- вывод в поле Данные-----------------------------// if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==3 ) sda_out <= data_1[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==3 ) sda_out <= data_1[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==3 ) sda_out <= data_1[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==3 ) sda_out <= data_1[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==3 ) sda_out <= data_1[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==3 ) sda_out <= data_1[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==3 ) sda_out <= data_1[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==3 ) sda_out <= data_1[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==3 & new1 ) sda_out <= 1'b0; if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==2 ) sda_out <= data_2[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==2 ) sda_out <= data_2[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==2 ) sda_out <= data_2[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==2 ) sda_out <= data_2[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==2 ) sda_out <= data_2[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==2 ) sda_out <= data_2[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==2 ) sda_out <= data_2[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==2 ) sda_out <= data_2[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==2 ) sda_out <= 1'b0; if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==1 ) sda_out <= data_3[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==1 ) sda_out <= data_3[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==1 ) sda_out <= data_3[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==1 ) sda_out <= data_3[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==1 ) sda_out <= data_3[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==1 ) sda_out <= data_3[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==1 ) sda_out <= data_3[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==1 ) sda_out <= data_3[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==1 ) sda_out <= 1'b0; if ( bitcnt_transmit==3'h7 & new_bitcnt_transmit==0 ) sda_out <= CRCout[7]; if ( bitcnt_transmit==3'h6 & new_bitcnt_transmit==0 ) sda_out <= CRCout[6]; if ( bitcnt_transmit==3'h5 & new_bitcnt_transmit==0 ) sda_out <= CRCout[5]; if ( bitcnt_transmit==4'h4 & new_bitcnt_transmit==0 ) sda_out <= CRCout[4]; if ( bitcnt_transmit==3'h3 & new_bitcnt_transmit==0 ) sda_out <= CRCout[3]; if ( bitcnt_transmit==3'h2 & new_bitcnt_transmit==0 ) sda_out <= CRCout[2]; if ( bitcnt_transmit==1 & new_bitcnt_transmit==0 ) sda_out <= CRCout[1]; if ( bitcnt_transmit==0 & new_bitcnt_transmit==0 ) sda_out <= CRCout[0]; if ( bitcnt_transmit==4'hf & new_bitcnt_transmit==0 ) sda_out <= 1'b0;
92 end end assign tris =(!new1) ? bitctk : 1'b1; wire tristate_usl1; assign tristate_usl = (new1 & incycle) ? bit_DATA : tris; assign tristate_usl_scl = (new1) ? 1'b1: 1'b0; assign dataout1= data; //<=== mojno dobavit' uslovie
//-------------------------------Бит который показывет где входная CRC----------------------// always @(posedge bit_ACK) begin if (new_bitcnt == 9'd255 ) cnt_crc <= number_sensor; else if (cnt_crc == 6'd2) cnt_crc=6'd2; else cnt_crc = cnt_crc-1'b1; end
//--------------------------Выходная последовательность для расчета CRC ---------------// assign inv =sda_in1 ^ CRCin[7] ; assign inv1 = (new1) ? sda_out ^ CRCout[7] : 1'b0 ;
//assign inv2 = (start_stop_sob) ? sda_out ^ CRCsob[7] : 1'b0; wire [7:0] numbtcnt_or_value;
//assign numbtcnt_or_value
////-------------------------Расчет CRC------------------------//
//Расчет входного CRC ---------// always @(posedge clk) if (incycle ) begin
CRCin=1'b0; end else if (stopcrc) begin
CRCin[7] = CRCin[6];
CRCin[6] = CRCin[5];
CRCin[5] = CRCin[4];
CRCin[4] = CRCin[3];
CRCin[3] = CRCin[2];
CRCin[2] = CRCin[1] ^ inv;
CRCin[1] = CRCin[0] ^ inv;
CRCin[0] = inv; end
// ----Расчет выходного CRC-----// always @(posedge clk) if (new1 ) begin
CRCout=1'b0; end else if (stopcrc_ans) begin
CRCout[7] = CRCout[6];
CRCout[6] = CRCout[5];
CRCout[5] = CRCout[4];
CRCout[4] = CRCout[3];
CRCout[3] = CRCout[2];
CRCout[2] = CRCout[1] ^ inv1;
CRCout[1] = CRCout[0] ^ inv1;
CRCout[0] = inv1; end always @(negedge clk) begin if (new_bitcnt== number_or_value2 +1'b1)//numb_bit_cnt crc_calc <= CRCin; end always @(negedge clk) begin if (cnt_crc == 6'h06) crcsoob <= CRCin; else crcsoob=crcsoob; end
//--------------------------------------------------------------------- -------------// always @(bitcnt) begin
93 if (new_bitcnt== number_or_value2 +1'b1 & bitcnt< 4'hf ) stopcrc=1'b1; else stopcrc=1'b0; end always @(negedge clk) begin if (new_bitcnt_transmit==3'h0 ) stopcrc_ans=1'b1; else stopcrc_ans=1'b0; end
//-------------------- nomer baita gde crc-------------------------// always@ (clk) if (incycle) begin numb_bit_cnt=9'd256-number_sensor; end
//---------------------Расчет принятого CRC -----------------------// always@ (negedge clk) begin if (new_bitcnt==numb_bit_cnt) crc_reciv<= mem_0 ; end
//-------------------------------Флаги CRC-----------------------//
//--------flag sovpadenia crc--// always@(negedge clk_all) if (crc_reciv ==crc_calc & cnt_mem2 > numb_bit_cnt) ///& cnt_mem2 > numb_bit_cnt ) begin crceq=1'b1; end else begin crceq=1'b0; end
//--------Проверка рассчитанного CRC с принятым --// always@(negedge clk_all) if (crc_reciv !=crc_calc & incycle) begin crcneq=1'b1; end else begin crcneq=1'b0; end always@( negedge clk_all) if (bitcnt_transmit==4'h7 & new_bitcnt_transmit==4'h8) begin stopans=1'b1; end else begin stopans=1'b0; end always@( posedge crceq or negedge stopans) begin stopans1=stopans1; end always@( stopans1) //negedge incycle) //or negedge stopans ) if (type_query[3:2]==2'b01 & !event1 & crceq ) begin start_answer_sensors=1'b1; end else begin start_answer_sensors=1'b0; end assign scl_out = ( new1 ) ? clk: 1'b1; endmodule
//-------------------------------------------------Модуль ТОДМ--// module TODMmy(N_sens,sensor1_1,sensor2_1,sensor3_1,sensor4_1,sensor5_1, sensor6_1,sensor7_1,sensor8_1,sensor1_1a,sensor2_1a,sensor3_1a,sensor4_1a, sensor5_1a,sensor6_1a,sensor7_1a,sensor8_1a,clk,event1, dat1,dat2,dat3,cnt_numb_event,linefree);
////parameters/////////////////////
///////////////////////////////////
94 reg [3:0] nomer=8'd2;////////////// reg rejim=1'b0;//////////////////// reg sensormodesoftreg;///////////// reg choose_h_s;////////////////////
/////////////////////////////////// Пороговые значения------------// reg [15:0] sensorlim1=16'h88;////// reg [15:0] sensorlim2=16'h88;////// reg [15:0] sensorlim3=16'h88;////// reg [15:0] sensorlim4=16'h88; ///// reg [15:0] sensorlim5=16'h88;////// reg [15:0] sensorlim6=16'h88;////// reg [15:0] sensorlim7=16'h88;////// reg [15:0] sensorlim8=16'h88;////// input wire linefree; output reg [7:0] cnt_numb_event=1'b0; input [7:0] N_sens; reg sobitye; input clk; input wire sensor1_1; input wire sensor2_1; input wire sensor3_1; input wire sensor4_1; input wire sensor5_1; input wire sensor6_1; input wire sensor7_1; input wire sensor8_1; input wire[15:0] sensor1_1a; input wire[15:0] sensor2_1a; input wire[15:0] sensor3_1a; input wire[15:0] sensor4_1a; input wire[15:0] sensor5_1a; input wire[15:0] sensor6_1a; input wire[15:0] sensor7_1a; input wire[15:0] sensor8_1a;
/////////////////////////// reg sensormode1=1'b0;
/////////////////////////// wire modesensorst; assign modesensors= ( choose_h_s) ? sensormode1: sensormodesoftreg; reg flagifadc1; reg flagifadc2; reg flagifadc3; reg flagifadc4; reg flagifadc5; reg flagifadc6; reg flagifadc7; reg flagifadc8; reg [15:0] sensorreg1; reg [15:0] sensorreg2; reg [15:0] sensorreg3; reg [15:0] sensorreg4; reg [15:0] sensorreg5; reg [15:0] sensorreg6; reg [15:0] sensorreg7; reg [15:0] sensorreg8; reg [2:0] cnt2=0; reg [3:0] cnt3=1'b0; reg start_stop_sob; reg stopcrc_sob; reg flag1; reg flag2; reg flag3; reg flag4; reg flag5; reg flag6; reg flag7; reg flag8; output reg [7:0] dat1; output reg [7:0] dat2; output reg [7:0] dat3; reg [7:0] dat4; reg [7:0] numb; reg [15:0] quiz_freq=16'd65534;///// reg [7:0] data1last=0; reg datcheck; output wire event1; wire sobitye1; assign event1= (rejim) ? sobitye : sobitye1;
95 always @(negedge sobitye) begin data1last<= cnt3+1; end always @(negedge clk) begin if( sobitye & data1last==dat1) datcheck<=1; else datcheck<=0; end parameter swnsormode1=1'b1; wire [7:0] N_sens1; assign N_sens1 = N_sens; reg [3:0] check; always @(negedge sobitye) begin check <=cnt3; end assign sobitye1=(check!=cnt3+1'b1 & !datcheck )? sobitye : 1'b0;
//-----------------------Вывод значений с датчиков к ОДСК--------// always@ (negedge clk) begin if (sensormode1 & !sobitye ) begin case (N_sens1)
7'b0001 : begin dat1 <= N_sens1; dat2<= sensorreg1[15:8]; dat3<= sensorreg1[7:0]; end
7'b0010 : begin dat1 <= N_sens1; dat2<= sensorreg2[15:8]; dat3<= sensorreg2[7:0]; end
7'b0011 : begin dat1 <= N_sens1; dat2<= sensorreg3[15:8]; dat3<= sensorreg4[7:0]; end
7'b0100 : begin dat1 <= N_sens1; dat2<= sensorreg4[15:8]; dat3<= sensorreg4[7:0]; end
7'b0101 : begin dat1 <= N_sens1; dat2<= sensorreg5[15:8]; dat3<= sensorreg5[7:0]; end
7'b00110: begin dat1 <= N_sens1; dat2<= sensorreg6[15:8]; dat3<= sensorreg6[7:0]; end
7'b0111 : begin dat1 <= N_sens1; dat2<= sensorreg7[15:8]; dat3<= sensorreg7[7:0]; end
7'b1000 : begin dat1 <= N_sens1; dat2<= sensorreg8[15:8]; dat3<= sensorreg8[7:0]; end endcase end if (sobitye & sensormode1) begin case (cnt3)
7'b000: begin
96 dat1 <= cnt3+1; dat2<= sensorreg1[15:8]; dat3<= sensorreg1[7:0]; end
7'b0001 : begin dat1 <= cnt3+1; dat2<= sensorreg2[15:8]; dat3<= sensorreg2[7:0]; end
7'b0010 : begin dat1 <= cnt3+1; dat2<= sensorreg3[15:8]; dat3<= sensorreg3[7:0]; end
7'b0011 : begin dat1 <= cnt3+1; dat2<= sensorreg4[15:8]; dat3<= sensorreg4[7:0]; end
7'b0100 : begin dat1 <= cnt3+1; dat2<= sensorreg5[15:8]; dat3<= sensorreg5[7:0]; end
7'b0101 : begin dat1 <= cnt3+1; dat2<= sensorreg6[15:8]; dat3<= sensorreg6[7:0]; end
7'b00110: begin dat1 <= cnt3+1; dat2<= sensorreg7[15:8]; dat3<= sensorreg7[7:0]; end
7'b0111 : begin dat1 <= cnt3+1; dat2<= sensorreg8[15:8]; dat3<= sensorreg8[7:0]; end endcase end if (!sobitye & !sensormode1) begin dat1 <= N_sens1; dat2<= 1'b0; dat3<= 1'b0; end if (sobitye & !sensormode1) begin dat1 <= cnt3+1; dat2<= 1'b0; dat3<= 1'b0; end end always@ (negedge clk) begin if (sensor1_1== 1'b1 ) flag1=1'b1; else flag1=1'b0; if (sensor2_1== 1'b1) flag2=1'b1; else flag2=1'b0; if (sensor3_1== 1'b1) flag3=1'b1; else flag3=1'b0; if (sensor4_1== 1'b1) flag4=1'b1; else flag4=1'b0; if (sensor5_1== 1'b1) flag5=1'b1; else flag5=1'b0; if (sensor6_1== 1'b1)
97 flag6=1'b1; else flag6=1'b0; if (sensor7_1== 1'b1) flag7=1'b1; else flag7=1'b0; if (sensor8_1== 1'b1) flag8=1'b1; else flag8=1'b0; end always@ (negedge clk) begin if (cnt2==1'b0 )//|| linefree) cnt2=quiz_freq; else if (!linefree) cnt2=cnt2; else cnt2= cnt2-1'b1; end always@ (posedge cnt2[nomer]) begin if (cnt3==3'd7 ) cnt3=1'b0; else cnt3= cnt3+1'b1; end always @( negedge clk) begin if ( & cnt27'd0 )//sobitye start_stop_sob=1'b1 ; else start_stop_sob=1'b0 ; end always @(negedge clk) begin if (cnt2< 7'd9 & start_stop_sob ) stopcrc_sob=1'b1; else stopcrc_sob=1'b0; end wire stop_sobitye; always @( negedge clk) begin if (sobitye & cnt27'd0 ) start_stop_sob=1'b1 ; else start_stop_sob=1'b0 ; end
//---------------------------------------wire flag adc or comporator assign flagadc_or_comp1 = (sensormode1) ? flagifadc1 : flag1; assign flagadc_or_comp2 = (sensormode1) ? flagifadc2 : flag2; assign flagadc_or_comp3 = (sensormode1) ? flagifadc3 : flag3; assign flagadc_or_comp4 = (sensormode1) ? flagifadc4 : flag4; assign flagadc_or_comp5 = (sensormode1) ? flagifadc5 : flag5; assign flagadc_or_comp6 = (sensormode1) ? flagifadc6 : flag6; assign flagadc_or_comp7 = (sensormode1) ? flagifadc7 : flag7; assign flagadc_or_comp8 = (sensormode1) ? flagifadc8 : flag8;
//----------------------------------------zapolnenenie registrov always @(posedge clk) begin sensorreg1 <= sensor1_1a; sensorreg2 <= sensor2_1a; sensorreg3 <= sensor3_1a; sensorreg4 <= sensor4_1a; sensorreg5 <= sensor5_1a; sensorreg6 <= sensor6_1a; sensorreg7 <= sensor7_1a; sensorreg8 <= sensor8_1a; end
//-------------------------------------flagifadc-------------// always@(posedge clk) begin if (sensor1_1a > sensorlim1)
98 flagifadc1<=1'b1; else flagifadc1<=1'b0; if (sensor2_1a > sensorlim2) flagifadc2<=1'b1; else flagifadc2<=1'b0; if (sensor3_1a > sensorlim3) flagifadc3<=1'b1; else flagifadc3<=1'b0; if (sensor4_1a > sensorlim4) flagifadc4<=1'b1; else flagifadc4<=1'b0; if (sensor5_1a > sensorlim5) flagifadc5<=1'b1; else flagifadc5<=1'b0; if (sensor6_1a > sensorlim6) flagifadc6<=1'b1; else flagifadc6<=1'b0; if (sensor7_1a > sensorlim7) flagifadc7<=1'b1; else flagifadc7<=1'b0; if (sensor8_1a > sensorlim8) flagifadc8<=1'b1; else flagifadc8<=1'b0; end
//---------------------------------------schetchic ? so-----------// always@(posedge sobitye) begin cnt_numb_event <= cnt_numb_event+7'd1; end
//------------------------------generit sobitye always @(cnt2[nomer])
//if (check!=cnt3+1) begin case (cnt3) //--------dobavit vmesto flaga flag comporator or adc
4'h0: sobitye <= flagadc_or_comp1;//flag 1 etc
4'h1: sobitye <= flagadc_or_comp2;
4'h2: sobitye <= flagadc_or_comp3;
4'h3: sobitye <= flagadc_or_comp4;
4'h4: sobitye <= flagadc_or_comp5;
4'h5: sobitye <= flagadc_or_comp6;
4'h6: sobitye <= flagadc_or_comp7;
4'h7: sobitye <= flagadc_or_comp8;
////chtenie s datchika endcase end endmodule
//----------------------Модуль РПО--------------------------// module RPOmy (clk,dat4,dat5,dat6,value,data_RPO,incycle,cnt_RPO, read_int_mem,write_success,select_mem,memerror,IOout1, IOout2,
IOout3,IOout4,nCE1_1,nCE2_1,nOE_1, nCE1_2,nCE2_2,nOE_2,nCE1_3, nCE2_3,nOE_3, nCE1_4,nCE2_4,nOE_4,clk_out_memrr2u,nCS_1,nWP_1, nCS_2,nWP_2, nCS_3,nWP_3, nCS_4,nWP_4,SO,SI1,SI2,SI3,SI4,PIn1,
PIn2,PIn3,PIn4, nCS_1,nWP_1,nCS_2,nWP_2,nCS_3,nWP_3,nCS_4,nWP_4, clk_out_memrr2u,ADDR, enbufIO1, enbufIO2
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