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ВКР Магистра. Программный сложно-функциональный блок


НазваниеПрограммный сложно-функциональный блок
Дата08.10.2019
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,enbufIO3,enbufIO4);
////////////////// parameter M=8;// OR 3 //----Объем сегмента------------------------// parameter K=0;//--SELECT MODE 1/0 166PP2Y/166RE014 reg [7:0] value2=8'd222; parameter M1=(3*M+3)*K ; //---only for erase in 166PP2Y parameter M2=(3*M+6 + 8*M)*K+M*!K;// value byte for write parameter M3=(3*M+6 + 8*M)*K+ M*!K;//value byte for read parameter A= M1+M2+M3;//all bytes parameter N1= A-M1; parameter N2= N1-M2; parameter N3= N2-M2; parameter T= 256-A;
/////////////////Параметры для 1661рр2у /////////////////

99 reg [7:0] SI_start_wr_er=8'd06;/////////////////// reg [7:0] SI_select_mode=8'h20;/////////////////// reg [7:0] SI_select_mode_wr =8'h92;/////////////// reg [7:0] SI_select_mode_read =8'h03;////////////// output wire clk_out_memrr2u; output reg[7:0] dat4; output reg[7:0] dat5; output reg[7:0] dat6; output reg write_success; output reg memerror; output wire [7:0] IOout1; output wire [7:0] IOout2; output wire [7:0] IOout3; output wire [7:0] IOout4;
//Выходы для PE014 output wire nCE1_1; output wire nCE2_1; output wire nOE_1; output wire nCE1_2; output wire nCE2_2; output wire nOE_2; output wire nCE1_3; output wire nCE2_3; output wire nOE_3; output wire nCE1_4; output wire nCE2_4; output wire nOE_4;
//--Выходы для PP2Y output wire nCS_1; output wire nWP_1; output wire nCS_2; output wire nWP_2; output wire nCS_3; output wire nWP_3; output wire nCS_4; output wire nWP_4; output reg SO =1'b0; output wire [16:0] ADDR; output wire enbufIO1; output wire enbufIO2; output wire enbufIO3; output wire enbufIO4; input read_int_mem; input wire [7:0] PIn1; input wire [7:0] PIn2; input wire [7:0] PIn3; input wire [7:0] PIn4; input clk; input wire [2:0] select_mem; input wire [8:0] cnt_RPO; input wire incycle; input wire [7:0] data_RPO; input wire [7:0] value; input wire SI1; input wire SI2; input wire SI3; input wire SI4; reg [7:0] cnter=8'd0; wire[2:0] flag; wire[2:0] flagn; wire datain1; reg [8:0] cnt_mem2=A; reg Cselect1_1=1'b0; reg Cselect1_2=1'b0; reg Cselect1_3=1'b0; reg Cselect1_4=1'b0; reg [7:0] cnt_mem1=1'b0; reg cselectall1; reg [7:0] timetostopinp=3; reg [7:0] timetostopcnt=3; reg stopread; reg [9:0] cnt4=8'd252; reg [1:0]cnt5; reg [7:0] datainall; reg [7:0] n1; reg [7:0] n2; reg [7:0] n3; reg [7:0] data_reg;
100 reg [7:0] data; reg [7:0] cnt_sector=1'b0; reg [7:0] data_reg2; reg [7:0 ]cnt_mem10; reg [8:0 ]cnt_mem11=9'd256; reg [7:0] cnt_M=8'd255; reg [7:0] addr_in_reg=8'd253; reg [7:0] addr_out_reg=8'd253; wire[7:0] datamem; wire[7:0] addrmem; assign flag[0]= ( N1 <= cnt_mem2 && cnt_mem2 < A )? 1'b1:1'b0; assign flag[1]= (cnt_mem2 < N1 && N2 <= cnt_mem2 )? 1'b1:1'b0; assign flag[2]= (cnt_mem2 < N2 )? 1'b1:1'b0;////////////////////////// assign nCSn= (cnt_mem2== N1-2 & K || cnt_mem2== N2-1 & K || cnt_mem2== A-2 & K ) ? 1'b1 : 1'b0; assign nCS= (flagn[0] & K || flagn[1] & K || flagn[2] & K ) ? nCSn : 1'b1 ; assign nWP= (flagn[0] & K || flagn[1] & K || flagn[2] & K ) ? 1'b1 : 1'b0 ; assign clk_out_memrr2u = (!nCS & K) ? clk: 1'b0; assign OK= (value2< cnt_M & K | value2 2'b01 : Cselect1_1 <= 1'b1;
2'b10 : Cselect1_2 <= 1'b1;
2'b11 : Cselect1_3 <= 1'b1;
3'b100:Cselect1_4 <= 1'b1; endcase end wire [3:0] cselectall; assign cselectall ={Cselect1_1,Cselect1_2,Cselect1_3,Cselect1_4}; always @(negedge clk) begin case (cselectall )
4'b0001 : datainall <= SI1;
4'b0010 : datainall <= SI2;
4'b0100 : datainall <= SI3;
4'b1000 : datainall <= SI4; endcase end always @(negedge clk )//////////////znachenie mb zamenit[] if(read_int_mem | !OK )///| cnt_mem2 <=9'd216) //value ) begin cnt_mem1 <= 4'h8; end else begin if(cnt_mem1==1'b0 ) begin cnt_mem1 <= 4'h7; end else cnt_mem1 <= cnt_mem1 - 4'h1; end always @(posedge cnt_mem1[2]) if( read_int_mem | cnt_mem2==9'd0 ) begin cnt_mem2 <= A; // end else begin if(data!=datainall) //<-----------------Проверка правильности записи в RAM-// begin cnt_mem2 <= cnt_mem2; end else cnt_mem2 <= cnt_mem2 - 4'h1; end reg wrout1; wire [7:0]addr_out;
101 wire [7:0]addr_out2; wire [7:0]addr_out3; reg [1:0 ] cnt_mem0; wire [7:0]addr_out4; wire [7:0]addr_out5; reg [7:0]cnt_N=8'd253;///t0 255
//--------------------------------------------------------------- assign addr_out5= (flag[2] & !K) ? addr_in_reg: 1'b0; assign addr_out4 = (flag[1] & !K ) ? addr_out_reg : addr_out5; assign addr_out3 = (flag[2] & K ) ? cnt_M-1 : addr_out4; assign addr_out2 = (flag[1] & K ) ? cnt_N-1 : addr_out3; assign addr_out = (wrout1 ) ? cnt_RPO : addr_out2;
//-------------------write enable-----------------// always@ (negedge clk) if (cnt_mem2 <= 9'd260 & incycle)//// dobavit uslovie zapisi begin wrout1 <= 1'b1; end else begin wrout1 <= 1'b0; end wire [7:0] rdaddress_aint;
//wire [7:0] rdaddress_bint; reg [7:0] data_in_reg ; reg [7:0] data_out_reg; always @(cnt_mem2) begin if (!K) begin if ( flag[1] ) addr_out_reg=addr_out_reg-1'b1; else addr_out_reg= addr_out_reg; end end always @( cnt_mem2) begin if (!K) begin if ( flag[2] )addr_in_reg=addr_in_reg-1'b1; else addr_in_reg= addr_in_reg; end end always @(posedge clk) if (read_int_mem) begin cnt4=8'd252; end else if (cnt4<= cnt_mem2 |cnt4 == value+1'b1 ) begin cnt4=cnt4; end else //if (numb_bit_cnt <= cnt_mem2 & numb_bit_cnt <= cnt_mem2) begin cnt4=cnt4-3'h4; end
//---cnt kotoriy zapisivaet adres iz v tri-----------// always @( cnt_mem2) if (read_int_mem| cnt_mem2 == value | cnt5==1'b1) begin cnt5=3'd3; end else begin cnt5=cnt5 -1'b1; end always@( datamem)//---sdelat esli posledniy dlya zapisi to flag obnulenia---// if (cnt_mem2==9'd259 ) begin cnt_sector=1'b0; end
102 else if (cnt_mem2 > value) begin cnt_sector=cnt_sector+1'b1; end
//-------------------------------------- ---------------------------// always@(negedge clk) if ( incycle & !OK ) begin write_success=1'b1; end else begin write_success=1'b0; end always @(posedge clk ) if (timetostopcnt==0) begin memerror=1'b1; end else begin memerror=1'b0; end always @(negedge clk) begin if (memerror) begin dat4<=cnt_sector; dat5<= select_mem; dat6<=1'b0; end if (write_success) begin dat4<=(8'd255-value)-3'd3; dat5<= 1'b0; dat6<=1'b0; end end
//-------------------------Внутренняя Память ПЛИС-------------------// ram rammy(
.address(addr_out),
.clock(clk),
.data(data_RPO),
.wren(wrout1),
.q (rdaddress_aint));
//-------------------------------------------------------------------- assign flagn[0]= ( 9'd77< cnt_mem2 )? flag[0]:1'b0; assign flagn[1]= (value2////////////////////////////////////////////////////// wire [20:0] addrcount= {n1[3:0], n2[7:0],n3[7:0] }; reg [19:0] addrcount_reg; reg [7:0] cnt_memnm=10; always @ (negedge cnt5[0]) //5 begin if ( cnt_mem2 > A-7 & K ) addrcount_reg<=addrcount; else if ( cnt_mem2==A-M1-1 & K ) addrcount_reg= addrcount_reg-(M-1); else addrcount_reg=addrcount_reg+1'b1; end wire [19:0] addrcount_reg_m ; assign addrcount_reg_m= addrcount_reg-4'd4; reg[19:0] addrcount_regN; reg[19:0] addrcount_regT; wire [7:0] IOout; assign ADDR= (flag[1] ) ? addrcount_regN-1'b1 : addrcount_regT-1'b1; assign IOout [7:0]= (flag[1] & cnt_mem1< 5'd6 ) ? rdaddress_aint : 1'bz; assign IOout1 = (Cselect1_1) ? IOout : 1'bz ; assign IOout2 = (Cselect1_2) ? IOout : 1'bz ; assign IOout3 = (Cselect1_3) ? IOout : 1'bz ; assign IOout4 = (Cselect1_4) ? IOout : 1'bz ;
103 always @ (addr_out_reg or cnt_RPO) //5 begin if ( addr_out_reg==8'd253 ) addrcount_regN<=addrcount; else addrcount_regN=addrcount_regN+1'b1; end always @ (addr_in_reg or cnt_RPO) //5 begin if ( addr_in_reg==8'd253 ) addrcount_regT<=addrcount; else addrcount_regT=addrcount_regT+1'b1; end reg [19:0] ADDR_rr2u1; reg [19:0] ADDR_rr2u2; reg [19:0] ADDR_rr2u3;
//-----------------------------------------------Вывод адреса ----// always @ (negedge clk) if ( read_int_mem) begin if ( flag[0] & cnt_mem2 ==A-9'd1 || flag[1] & cnt_mem2 ==A- M1-9'd1 & K ) begin if (cnt_mem1==3'h7 ) SO<= SI_start_wr_er [7]; if (cnt_mem1==3'h6 ) SO<= SI_start_wr_er [6]; if (cnt_mem1==3'h5 ) SO<= SI_start_wr_er [5]; if (cnt_mem1==3'h4 ) SO<= SI_start_wr_er [4]; if (cnt_mem1==3'h3 ) SO<= SI_start_wr_er [3]; if (cnt_mem1==3'h2) SO<= SI_start_wr_er [2]; if (cnt_mem1==3'h1 ) SO<= SI_start_wr_er [1]; if (cnt_mem1==3'h0) SO<= SI_start_wr_er [0]; end if (flag[1] & cnt_mem2 ==A- M1-9'd3 & K) begin//---------zapis if (cnt_mem1==3'h7) SO<= SI_select_mode_wr [7]; if (cnt_mem1==3'h6) SO<= SI_select_mode_wr [6]; if (cnt_mem1==3'h5) SO<= SI_select_mode_wr [5]; if (cnt_mem1==3'h4) SO<= SI_select_mode_wr [4]; if (cnt_mem1==3'h3) SO<= SI_select_mode_wr [3]; if (cnt_mem1==3'h2) SO<= SI_select_mode_wr [2]; if (cnt_mem1==3'h1) SO<= SI_select_mode_wr [1]; if (cnt_mem1==3'h0) SO<= SI_select_mode_wr [0]; end if ( flag[0] & cnt_mem2 ==A-3 & K) begin if (cnt_mem1==3'h7) SO<= SI_select_mode [7]; if (cnt_mem1==3'h6) SO<= SI_select_mode [6]; if (cnt_mem1==3'h5) SO<= SI_select_mode [5]; if (cnt_mem1==3'h4) SO<= SI_select_mode [4]; if (cnt_mem1==3'h3) SO<= SI_select_mode [3]; if (cnt_mem1==3'h2) SO<= SI_select_mode [2]; if (cnt_mem1==3'h1) SO<= SI_select_mode [1]; if (cnt_mem1==3'h0) SO<= SI_select_mode [0]; end if ( flag[2] & cnt_mem2 ==A-M1-M2-1 & K) begin if (cnt_mem1==3'h7) SO<= SI_select_mode_read [7]; if (cnt_mem1==3'h6) SO<= SI_select_mode_read [6]; if (cnt_mem1==3'h5) SO<= SI_select_mode_read [5]; if (cnt_mem1==3'h4) SO<= SI_select_mode_read [4]; if (cnt_mem1==3'h3) SO<= SI_select_mode_read [3]; if (cnt_mem1==3'h2) SO<= SI_select_mode_read [2]; if (cnt_mem1==3'h1) SO<= SI_select_mode_read [1]; if (cnt_mem1==3'h0) SO<= SI_select_mode_read [0]; end if (flag[0] & cnt_mem2 ==A-4 & K || flag [2] & cnt_mem2 ==A-M1-M2-2 & K ) begin if (cnt_mem1==3'h7 ) SO<= n1 [7]; if (cnt_mem1==3'h6 ) SO<= n1 [6]; if (cnt_mem1==3'h5 ) SO<= n1 [5]; if (cnt_mem1==3'h4 ) SO<= n1 [4]; if (cnt_mem1==3'h3 ) SO<= n1 [3]; if (cnt_mem1==3'h2 ) SO<= n1 [2]; if (cnt_mem1==3'h1 ) SO<= n1 [1]; if (cnt_mem1==3'h0 ) SO<= n1 [0]; end if ( flag[0] & cnt_mem2 ==A-5 & K || flag [2] & cnt_mem2 ==A-M1-M2-3 & K) begin if (cnt_mem1==3'h7 ) SO<= n2 [7];
104 if (cnt_mem1==3'h6 ) SO<= n2 [6]; if (cnt_mem1==3'h5 ) SO<= n2 [5]; if (cnt_mem1==3'h4 ) SO<= n2 [4]; if (cnt_mem1==3'h3 ) SO<= n2 [3]; if (cnt_mem1==3'h2 ) SO<= n2 [2]; if (cnt_mem1==3'h1 ) SO<= n2 [1]; if (cnt_mem1==3'h0 ) SO<= n2 [0]; end if ( flag[0] & cnt_mem2 ==A-6 & K || flag [2] & cnt_mem2 ==A-M1-M2-4 & K) begin if (cnt_mem1==3'h7 ) SO<= n3 [7]; if (cnt_mem1==3'h6 ) SO<= n3 [6]; if (cnt_mem1==3'h5 ) SO<= n3 [5]; if (cnt_mem1==3'h4 ) SO<= n3 [4]; if (cnt_mem1==3'h3 ) SO<= n3 [3]; if (cnt_mem1==3'h2 ) SO<= n3 [2]; if (cnt_mem1==3'h1 ) SO<= n3 [1]; if (cnt_mem1==3'h0 ) SO<= n3 [0]; end if ( flag[0] & cnt_mem2 <=A-7 & cnt5==2'd2 & K || flag[1] & cnt_mem2 ==A- M1-9'd4 & K) begin if (cnt_mem1==3'h7) SO<= 1'b0; if (cnt_mem1==3'h6) SO<= 1'b0; if (cnt_mem1==3'h5) SO<= 1'b0; if (cnt_mem1==3'h4) SO<= 1'b0; if (cnt_mem1==3'h3) SO<= addrcount_reg [19]; if (cnt_mem1==3'h2) SO<= addrcount_reg [18]; if (cnt_mem1==3'h1) SO<= addrcount_reg [17]; if (cnt_mem1==3'h0) SO<= addrcount_reg [16]; end if ( flag[0] & cnt_mem2 <=A-8 & cnt5==3'd1 & K|| flag[1] & cnt_mem2 ==A- M1-9'd5 & K ) begin if (cnt_mem1==3'h7) SO<= addrcount_reg [15]; if (cnt_mem1==3'h6) SO<= addrcount_reg [14]; if (cnt_mem1==3'h5) SO<= addrcount_reg [13]; if (cnt_mem1==3'h4) SO<= addrcount_reg [12]; if (cnt_mem1==3'h3) SO<= addrcount_reg [11]; if (cnt_mem1==3'h2) SO<= addrcount_reg [10]; if (cnt_mem1==3'h1) SO<= addrcount_reg [9]; if (cnt_mem1==3'h0) SO<= addrcount_reg [8]; end if ( flag[0] & cnt_mem2 <=A-9 & cnt5==3'd3 & K || flag[1] & cnt_mem2 ==A- M1-9'd6 & K) begin if (cnt_mem1==3'h7) SO<= addrcount_reg [7]; if (cnt_mem1==3'h6) SO<= addrcount_reg [6]; if (cnt_mem1==3'h5) SO<= addrcount_reg [5]; if (cnt_mem1==3'h4) SO<= addrcount_reg [4]; if (cnt_mem1==3'h3) SO<= addrcount_reg [3]; if (cnt_mem1==3'h2) SO<= addrcount_reg [2]; if (cnt_mem1==3'h1) SO<= addrcount_reg [1]; if (cnt_mem1==3'h0) SO<= addrcount_reg [0]; end
//------------------------- addrcount_reg_m if ( flag[1] & cnt_memnm==4'd11 & K ) begin if (cnt_mem1==3'h7) SO<= 1'b0; if (cnt_mem1==3'h6) SO<= 1'b0; if (cnt_mem1==3'h5) SO<= 1'b0; if (cnt_mem1==3'h4) SO<= 1'b0; if (cnt_mem1==3'h3) SO<= ADDR_rr2u2 [19]; if (cnt_mem1==3'h2) SO<= ADDR_rr2u2 [18]; if (cnt_mem1==3'h1) SO<= ADDR_rr2u2 [17]; if (cnt_mem1==3'h0) SO<= ADDR_rr2u2 [16]; end if ( flag[1] & cnt_memnm==4'd10 & K ) begin if (cnt_mem1==3'h7) SO<= ADDR_rr2u2 [15]; if (cnt_mem1==3'h6) SO<= ADDR_rr2u2 [14]; if (cnt_mem1==3'h5) SO<= ADDR_rr2u2 [13]; if (cnt_mem1==3'h4) SO<= ADDR_rr2u2 [12]; if (cnt_mem1==3'h3) SO<= ADDR_rr2u2 [11]; if (cnt_mem1==3'h2) SO<= ADDR_rr2u2 [10]; if (cnt_mem1==3'h1) SO<= ADDR_rr2u2 [9]; if (cnt_mem1==3'h0) SO<= ADDR_rr2u2 [8]; end if ( flag[1] & cnt_memnm==4'd9 & K ) begin if (cnt_mem1==3'h7) SO<= ADDR_rr2u2 [7]; if (cnt_mem1==3'h6) SO<= ADDR_rr2u2 [6]; if (cnt_mem1==3'h5) SO<= ADDR_rr2u2 [5]; if (cnt_mem1==3'h4) SO<= ADDR_rr2u2 [4]; if (cnt_mem1==3'h3) SO<= ADDR_rr2u2 [3]; if (cnt_mem1==3'h2) SO<= ADDR_rr2u2 [2]; if (cnt_mem1==3'h1) SO<= ADDR_rr2u2 [1]; if (cnt_mem1==3'h0) SO<= ADDR_rr2u2 [0];
105 end if (flag[1] & cnt_memnm<=7'd8 & K ) begin if (cnt_mem1==3'h7) SO<= rdaddress_aint [7]; if (cnt_mem1==3'h6) SO<= rdaddress_aint [6]; if (cnt_mem1==3'h5) SO<= rdaddress_aint [5]; if (cnt_mem1==3'h4) SO<= rdaddress_aint [4]; if (cnt_mem1==3'h3) SO<= rdaddress_aint [3]; if (cnt_mem1==3'h2) SO<= rdaddress_aint [2]; if (cnt_mem1==3'h1) SO<= rdaddress_aint [1]; if (cnt_mem1==3'h0) SO<= rdaddress_aint [0]; end end always @ ( cnt_mem2) begin if ( !flag[1] | flag[1]& cnt_mem2> N1-4 |!K ) cnt_memnm<= 13; else if (cnt_memnm==1'b0) cnt_memnm<= 12; else cnt_memnm<= cnt_memnm-1'b1; end reg [7:0] cnt_memnm2; always @ ( cnt_mem2) begin if ( !flag[2] | flag[2]& cnt_mem2> N2-4 |!K ) cnt_memnm2<= 12; else if (cnt_memnm2==1'b0) cnt_memnm2<= 11; else cnt_memnm2<= cnt_memnm2-1'b1; end always @ ( cnt_memnm) begin if (flag[1] & cnt_memnm<=4'd8 ) cnt_N = cnt_N-1'b1; else cnt_N=cnt_N; end always @ ( cnt_mem2) begin if (flag[2] & cnt_mem2<=A-M1-M2-6 & K) cnt_M = cnt_M-1'b1; else cnt_M=cnt_M; end wire R=1'b1; assign INSI = (flagn [2] & cnt_mem2 <=A-M1-M2-7 & K) ? SI2 : 1'bz ; assign R=(cnt_mem2 <= N2 ) ? 1'b0 : 1'b1 ; reg [7:0] INSI8; always @ ( cnt_mem1) begin if(flag[2] & K) INSI8[cnt_mem1] <= INSI; end
//flag[1] & cnt_mem2 <=A- M1-9'd6 & A- M1-9'd14 <= cnt_mem2 always @ (negedge clk) begin if (cnt_RPO==9'd255) n1<=data_RPO ; if (cnt_RPO==9'd254) n2<=data_RPO ; if (cnt_RPO==9'd253) n3<=data_RPO ; end wire nCE1; assign nCE1= (flag[1] & !K & OK || flag[2] & !K & OK ) ? 1'b0 : 1'b1 ;
106 assign nCE2= (flag[1] & !K & cnt_mem2==A-M2 || flag[2] & !K & cnt_mem2==A-M2 ) ? 1'b0 : 1'b1 ; assign nWE= (flag[1] & !K) ? 1'b0 : 1'b1 ; assign nOE= (flag[2] & !K) ? 1'b0 : 1'b1 ; assign nCE1_1= (Cselect1_1) ? nCE1 : 1'b0 ; assign nCE2_1= (Cselect1_1) ? nCE2 : 1'b0 ; assign nWE_1= (Cselect1_1) ? nWE: 1'b0 ; assign nOE_1= (Cselect1_1) ? nOE: 1'b0 ; assign nCE1_2= (Cselect1_2) ? nCE1 : 1'b0 ; assign nCE2_2= (Cselect1_2) ? nCE2 : 1'b0 ; assign nWE_2= (Cselect1_2) ? nWE: 1'b0 ; assign nOE_2= (Cselect1_2) ? nOE: 1'b0 ; assign nCE1_3= (Cselect1_3) ? nCE1 : 1'b0 ; assign nCE2_3= (Cselect1_3) ? nCE2 : 1'b0 ; assign nWE_3= (Cselect1_3) ? nWE: 1'b0 ; assign nOE_3= (Cselect1_3) ? nOE: 1'b0 ; assign nCE1_4= (Cselect1_4) ? nCE1 : 1'b0 ; assign nCE2_4= (Cselect1_4) ? nCE2 : 1'b0 ; assign nWE_4= (Cselect1_4) ? nWE: 1'b0 ; assign nOE_4= (Cselect1_4) ? nOE: 1'b0 ;
//------------------------for 1661ðð2ó assign nCS_1= (Cselect1_1 ) ? nCS : 1'b0 ; assign nWP_1= (Cselect1_1 ) ? nWP : 1'b0 ; assign nCS_2= (Cselect1_2 ) ? nCS : 1'b0 ; assign nWP_2= (Cselect1_2 ) ? nWP : 1'b0 ; assign nCS_3= (Cselect1_3 ) ? nCS : 1'b0 ; assign nWP_3= (Cselect1_3 ) ? nWP : 1'b0 ; assign nCS_4= (Cselect1_4 ) ? nCS : 1'b0 ; assign nWP_4= (Cselect1_4 ) ? nWP : 1'b0 ; assign Ktr= (flag[1] & cnt_memnm<=8'd11 & 8'd9 <=cnt_memnm | flag[2] & cnt_memnm2<=8'd11 &
8'd9 <=cnt_memnm2 ) ? 1'b1: 1'b0 ; reg [9:0] cnt_mem3; always @( posedge clk) begin cnt_mem3<= cnt_mem2 ; end reg[7:0] regA=8'd255; reg[7:0] regB=8'd255; reg[7:0] regC=8'd255; always @(negedge cnt5[0]) if (K) begin if (flagn[0]) regA<=regA-1'b1; else regA<=regA; end always @(negedge cnt5[0]) if (K) begin if (flagn[1]) regB<=regB-1'b1; else regB<=regB; end always @(negedge cnt5[0]) if (K) begin if (flagn[2]) regC<=regC-1'b1; else regC<=regC; end always @( regA) if (K) begin if (8'd253 <=regA )
ADDR_rr2u1 <=addrcount; else
ADDR_rr2u1=ADDR_rr2u1-1'b1; end always @( regB)
107 if (K) begin if (8'd253 <=regB )
ADDR_rr2u2 <=addrcount; else if (Ktr)
ADDR_rr2u2=ADDR_rr2u2-1'b1; end endmodule
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